The functional operation of a digital to analog converter (DAC) is well known. Generally, a DAC accepts a digital input signal and converts it into an analog output signal. The digital input signal has a range of digital codes which are converted into a continuous range of analog signal levels of the analog output signal. DACs are useful to interface digital systems to analog systems. Applications of DACs include video or graphic display drivers, audio systems, digital signal processing, function generators, digital attenuators, precision instruments and data acquisition systems including automated test equipment.
There are a variety of DACs available for converting digital input signals into analog output signals depending upon the desired conversion functionality. The variations in the DACs available may have different predetermined resolutions of a digital input signal, receive different encoded digital input signals, have different ranges of analog output signals using a fixed reference or a multiplied reference, and provide different types of analog output signals. Additionally there are a number of DAC performance factors to consider such as settling time, full scale transition time, accuracy or linearity, and a factor previously mentioned, resolution.
The digital input signal is a number of bits wide that defines the resolution, the number of output levels or quantization levels, and the total number of digital codes that are acceptable. If the digital input signal is m-bits wide, there are 2.sup.m output levels and 2.sup.m-1 steps between levels. The digital input signals may be encoded in straight binary, two's complement, offset binary, grey scale code, binary coded decimal or other digital coding. The range of analog output signal values usually depend upon an analog reference. The analog reference may be internally generated but is usually externally provided for precision. The analog output signal range may be proportional to the digital input signal over a fixed analog reference level as in a fixed reference DAC. Alternatively, the analog output signal may be the product of a varying input analog reference level and the digital code of the digital input signal as in multiplying DACs. The analog output signal may be unipolar ranging in either positive values or negative values or it may be bipolar ranging between both positive and negative output values. The analog output signal may be an analog voltage signal or an analog current signal.
Additionally, the type of electronic circuitry used to form a DAC varies as well. Bipolar junction transistor (BJT) technology, metal oxide semiconductor (MOS) technology or a combination thereof are used to construct DACs. BJT technology may be PNP technology with PNP transistors or NPN with NPN transistors or both, while MOS technology may be PMOS with P-channel field effect transistors (PFET), NMOS with N-channel field effect transistors (PFET) or CMOS technology having both PFETs and NFETs. Generally, BJT technology is preferable for constructing precision amplifiers because it has higher transconductance than CMOS technology. This results in lower offset for differential amplifiers. CMOS technology is preferable for constructing switches because it has nearly zero offset when used as a switch. This is so because PFETs and NFETs have virtually no gate current as compared to base current for PNP and NPN transistors of BJT technology. Integrated circuits or wafer fab manufacturing processes combining both BJT and CMOS technology, referred to as BICMOS circuits or processes, are used to provide BJT technology for amplifiers and CMOS technology for switches on the same integrated circuit.
Referring now to FIG. 1, a block diagram of a DAC 100 has a digital input signal DIN 101, a positive analog supply voltage level, AVref+ 104, and a negative analog supply voltage level, AVref- 105, in order to generate an analog voltage output signal, AVout 110. Alternatively DAC 100 can generate an analog current output signal with minor changes to its circuit configuration. To generate either type of analog output, the DAC 100 includes digital and analog power supplies. The digital power supply provided to DAC 100 is input across the positive digital supply terminal, VCC 102, and the negative digital supply terminal, DGND 103. The positive analog power supply provided to DAC 100 is input across the positive analog supply terminal, VDD 106, and the analog ground terminal, AGND 107. The negative analog power supply is input across the negative analog supply terminal, VSS 108, and the analog ground terminal, AGND 107.
For simplicity in discussion consider DAC 100 to be a fixed reference DAC such that the output voltage range of AVout 110 is a function of DIN 101 and the range of voltage is defined by the predetermined voltage levels of AVref+ 104 and AVref- 105. DIN 101 is m bits wide. The predetermined value of m represents the range of decimal numbers that DIN 101 will represent. The selected circuitry for DAC 100 varies depending upon a number of factors including power supply inputs and desired parameters of input and output signals. As illustrated in FIG. 1, DAC 100 includes a signal converter 112 and an amplifier or buffer 114. Some forms of DACs, specifically current output DACs, may not include the buffer 114 and require external amplification. Signal converter 112 converts DIN 101 into a form of analog signal VLADR 120 which is input to buffer 114. Buffer 114 buffers the analog signal VLADR 120 generated by the signal converter 112 from a load that may be coupled to AVout 110. The signal converter 112 includes a switched R-2R ladder 116 and a switch controller 118. Switch controller 118 controls switches within the switched R-2R ladder 116 to cause it to convert the value of DIN 101 into an analog signal.
As previously discussed, there are a number of DAC performance factors to consider including a DAC's accuracy or linearity. In measuring linearity of a DAC, the analog output AVout 110 from a DAC may be bipolar output voltages, positive unipolar output voltages or negative unipolar output voltages over the range of the digital input signal DIN 101. If a change in an analog voltage reference level is required to establish a zero point or a midpoint of the conversion range, it is referred to as an offset voltage. Differential linearity is the linearity between code transitions measuring the monotonicity of a DAC. If increasing code values of DIN results in increasing values of AVout, the DAC is monotonic, and if not, the DAC has a conversion error and is not monotonic. The linearity of a DAC is very important for accurate conversions and is usually specified in units of least significant bits (LSB) of DIN 101. Linearity of a DAC can vary over temperature, voltages, and from circuit to circuit. Additionally, DAC linearity becomes more important as the predetermined DAC resolution is increased, where the value of m is larger, and additional digital codes are desired to be converted. Furthermore, as the analog voltage reference level range between AVref+ 104 and AVref- 105 may be increased to accommodate additional resolution, it is desirable to maintain linearity in a DAC.
Referring now to FIG. 2, a prior art switched R-2R ladder 116 is illustrated. The switched R-2R ladder 116 is a 4 bit inverted R-2R ladder to provide an analog voltage output signal but may be easily expanded to m-bits with the addition of other intermediate R-2R switch legs and additional switch control lines. Alternatively, a non-inverted R-2R ladder could be used to provide an analog current output signal. Signals DBn/DBp 201, the switch control lines, are selectively controlled by the switch controller 118 in order to generate an analog voltage signal VLADR 120. DBn/DBp 201 switches ON and OFF NFETs 211-214 and PFETs 216-219 in conjunction with NFETs 236-239 in order to change the voltage division of the R-2R resistor network between AVref+ 104 and AVref- 105 and VLADR 120. Inverters 246-249 generate the inverter polarity of the switch control lines D4Bp-D1Bp 241-244 to control the NFETs 236-239 to form fully complementary switches with PFETs 216-219. NFET 211 and PFET 216/NFET 236 represent the most significant bit (MSB) of the DAC and can couple 8/16 of the reference voltage range to VLADR 120. NFET 212 and PFET 217/NFET 237 can couple 4/16 of the reference voltage range to VLADR 120. NFET 213 and PFET 218/NFET 238 can couple 2/16 of the reference voltage range to VLADR 120. NFET 214 and PFET 219/NFET 239 represent the LSB of the DAC and can couple 1/16 of the reference voltage range to VLADR 120. Thus, when the digital code is 1111, PFETs 216-219 and NFETs 236-239 are all ON and NFETs 211-214 are all OFF such that 15/16 of the reference voltage range is coupled to VLADR 120. When the digital code is 0000, NFETs 211-214 are all ON and PFETs 216-219 and NFETs 236-239 are all OFF such that no current flows between AVref+ 104 and AVref- 105 in a resistor and AVref- 105 is coupled to VLADR 120.
The circuit connections of the switched R-2R ladder 116 are now described. NFET 215 has its gate tied to terminal leg gate voltage signal, TLGV 235, such that it is constantly turned ON. The voltage level of TLGV 235 additionally provides switch resistance matching between NFETs and PFETs in the switched R-2R ladder 116. NFETs 211-215 have sources connected to AVref- 105 and drains respectively connected to first ends of resistors 220-224. PFETs 216-219 have sources connected to AVref+ 104 and drains respectively connected to first ends of resistors 220-223. NFETs 236-239 have sources respectively connected to the first ends of resistors 220-224 and drains connected to AVref+ 104. The gates of NFETs 211-214 are respectively connected to signals D4Bn-D1Bn 231-234 and gates of PFETs 216-219 are respectively connected to signals D4Bp-D1Bp 241-244. The inverters 246-249 have inputs respectively coupled to signals D4Bp-D1Bp 241-244 to generate the inverted polarity for coupling their outputs to the gates of NFETs 236-239 respectively. Signals D4Bn-D1Bn 231-234 and signals D4Bp-D1Bp 241-244 are collectively referred to as signals DBn/DBp 201 from switch controller 118. Resistors 220-223 each have a resistance value of 2R. Resistors 224-228 each having a resistance value of R are coupled in series together with a first end of resistor 228 coupled to VLADR 120. A second end of resistor 224 is coupled to a second end of resistor 225 at node 250 while a second end of resistor 220 is coupled to VLADR 120. Resistors 223, 225, and 226 each have an end coupled to node 251. Resistors 222, 226, and 227 each have an end coupled to node 252. Resistors 221, 227, and 228 each have an end coupled to node 253. The MSB leg of the switched R-2R ladder 116 is defined as NFET 211/PFET 216/NFET 236 and resistor 220, the LSB leg as NFET 214/PFET 219/NFET 239 and resistors 223 and 226, and the termination leg as NFET 215 and resistors 224-225. The intermediate legs of the switched R-2R ladder 116 are NFET 213/PFET 218/NFET238 and resistors 222 and 227 and NFET 212/PFET 217/NFET237 and resistors 221 and 228.
The PFET and NFET switches are binarilly weighted from LSB to MSB to adjust for differences in IDS drain to source current flow and maintain similar VDS voltage drops across drain to source. For example, if NFET 214/PFET 219/NFET 239 switches are weighted 1.times., NFET 213/PFET 218/NFET 238 switches are weighted 2.times., NFET 212/PFET 217/NFET 237 switches are weighted 8.times., and NFET 211/PFET 216/NFET 236 switches are weighted 16.times. in transistor size to reduce the RON of the transistors. This reduces user trimming for a drift that would otherwise be introduced by mismatched RON resistances when the transistor switches are turned ON and OFF.
As previously discussed, linearity of DAC 100 is important to accurately convert DIN 101 to AVout 110. In switching voltages in the switched R-2R ladder 116, PFETs 216-219, NFETs 236-239, and NFETs 211-215 are switched ON to operate in their linear region where drain to source voltage, VDS, is equivalent to drain to source current times the ON resistance of the transistor. VDS.apprxeq.IDS.times.RON. The drain to source voltage and drain to source current vary such that the ON resistance, RON, of the transistor may remain somewhat constant. However, if the drain to source voltage, VDS, of the PFET or NFET switches reaches higher levels, saturation first occurs and then breakdown. Saturation and breakdown are both nonlinear effects which are undesirable operating characteristics for the PFET and NFET switches. In saturation the resistance of the transistor varies up until a drain to source breakdown voltage is reached. In breakdown of a MOSFET, little change in drain to source voltage causes substantial increases in the drain to source current. In breakdown, NFET and PFET device resistance is very small and substantial damage may occur if the drain to source current is not limited. MOSFET transistor breakdown may also occur because excessive gate to source voltage, VGS, is applied across the gate and source of an NFET or PFET.
In order to increase breakdown voltages, alternate transistor technology may be used or alternate transistor manufacturing topology may be used. However, the trend in wafer manufacturing of transistors is to construct smaller devices to lower costs and increase margins for a given integrated circuit. Techniques to increase breakdown voltages usually result in undesirable side-effects increasing manufacturing costs such as increasing device sizes. It is desirable to use circuitry to avoid excessive gate to source voltage, VGS, and drain to source voltage, VDS, being applied to NFET and PFET switches of a DAC which might otherwise cause breakdown. While diode clamp circuitry may be used to avoid excessive gate to source voltages, this is not practical in a DAC because of the requirements of linearity. If diodes clamp the voltage applied to gates of the switches in the switched R-2R ladder, resistance mismatching and nonlinearities would result when clamping would occur.
High voltage DACs are desirable to accommodate increased resolution while lower manufacturing costs are maintained by use of smaller devices with lower breakdown voltages. In higher voltage DAC's, the DAC power supply range is larger and the analog voltage reference level range between AVref+ 104 and AVref- 105 may be increased to support the higher resolution and maintain substantial linearity in DACs. Also, in certain applications, such as automated test equipment (ATE), it is desirable to vary the AVref+ 104 and AVref- 105 analog voltage reference levels to provide differing DAC analog output levels. In order to accommodate the varying levels of analog voltage reference levels, DAC power supply voltages may need to vary over a range as well. The high voltage levels and variability in analog voltage reference levels increase the potential for breakdown of MOSFET transistors including the PFET and NFET switches of the R-2R ladder 116. Higher gate to source voltage, VGS, and drain to source voltage, VDS, may be placed upon a given MOSFET transistor in high voltage DACs if steps are not taken to alleviate these conditions.
Additionally, the digital input signal DIN 101 provided to DAC 100 may be TTL logic levels, CMOS logic levels or their low voltage equivalents such as LVTTL or LVCMOS. In the operation of high voltage DACs, it is desirable to convert the voltage levels received for a digital input signal DIN 101 into proper internal voltage levels for operation of the DAC 100 without breakdown. Because it is desirable to provide variable analog voltage reference levels which leads to varying power supply levels, the problem of providing level translation for proper operation of the DAC 100 is increased. It is desirable to provide level translation within high voltage DACs such that varying analog voltage reference levels and power supply levels are accommodated and proper linear operation is achieved without MOSFET transistor breakdown.